Digital Phase Locked Loops (DPLLs) may provide a low-power-small-area solution relative to old fashion (analog) PLLs. In a DPLL the phase offset between a Local Oscillator (LO) and a reference clock is measured by an analog-to-digital convertor called Time-to-Digital Converter (TDC). The measured phase is then compared to the required phase and the result is used to correct the LO frequency. Due to the conversion to the digital domain, the phase measurement may suffer from aliasing. Aliased out-of-band noises are interpreted as in-band-noise, which may cause the control loop to inject wrong ‘corrections’. These may cause actual in-band spurs that may limit the DPLL Phase-Noise (PN) performances.